Regviz

NXP Semiconductors /MIMXRT1021 /PGC /MEGA_PUPSCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as MEGA_PUPSCR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/MIMXRT1021/PGC/MEGA_PUPSCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SW0SW2ISO

Description

PGC Mega Power Up Sequence Control Register

Fields

SW

After a power-up request (pup_req assertion), the PGC waits a number of IPG clocks equal to the value of SW before asserting power toggle on/off signal (switch_b) to switch on power
SW2ISO

After asserting power toggle on/off signal (switch_b) to switch on power, the PGC waits a number of IPG clocks equal to the value of SW2ISO before negating isolation

Links

()

Register License

Copyright 2016-2020 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data